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the comparison frequency is obtained either from an on?hip crystal controlled oscillator, or from an external source. the oscillator frequency f ref or the comparison frequency f comp may be switched to the ref/comp output. this feature is ideally suited to providing the reference frequency for a second synthesiser such as in a double conversion tuner (see fig. 8). the synthesiser is controlled via an i 2 c bus, and responds to one of four programmable addresses which are selected by applying a specific voltage to the ?ddress?input. this feature enables two or more synthesisers to be used in a system. the device contains four switching ports p0?3 and a 5?evel adc. the output of the adc can be read via the i 2 c bus. the device also contains a varactor line disable and chargepump disable facility. applications complete 2.7ghz single chip system optimised for low phase noise description the SP5669 is a single chip frequency synthesiser designed for tuning systems up to 2.7ghz and offers step size compatible with dtt offset requirements. the rf preamplifier drives a divide by two prescaler which can be disabled for applications up to 2ghz, allowing direct interfacing with the programmable divider so enabling a step size equal to the comparison frequency. for applications up to 2.7ghz the divide by two is enabled, giving a step size of twice the comparison frequency. SP5669 2.7ghz i 2 c bus controlled synthesiser preliminary information ds4852 issue 2.1 may 1999 ordering information SP5669/kg/mp1s (tubes) SP5669/kg/mp1t (tape and reel) features complete 2.7ghz single chip system compatible with uk dtt offset requirements optimised for low phase noise selectable divide by two prescaler selectable reference division ratio selectable reference/comparison frequency output selectable charge pump current four selectable i 2 c bus address 5?evel adc pin compatible with the sp5658 3?ire bus controlled synthesiser and sp5659 i 2 c bus synthesiser and sp5659 i 2 c bus synthesiser esd protection; (normal esd handling procedures should be observed)
2 SP5669 preliminary information figure 1 - pin connections - top view 116 1 mp16 charge pump crystal ref/comp address sda scl port p3 port p2 drive vee rf input rf input vcc adc port p0 port p1 2 3 4 5 6 7 89 10 11 12 13 14 15 rf 1 bit 17 bit la tch 4 bit la tch and port interface i transceiver crystal pump drive address adc sda scl port p3 port p2 inputs 13 14 4 5 6 11 programmable divider pump reference divider phase comp 2 bit osc 2 1 16 v ee 15 12 v cc 9 8 7 2/1 13 bit count 4 bit count 4 bit 10 port p1 port p0 16/17 c1, c0 3 ref/comp 3 bit adc pe 5 bit la tch and mode control logic (see fig. 5) charge latch latch lock detect latch divide ra tio pre amp f l f pd /2 p0 test control power on detect por disable mode control c 2 charge (see fig. 3) f comp f ref f pd figure 2 - block diagram
3 SP5669 preliminary information electrical characteristics t amb = 20 c to +80 c, v cc = +4.5v to +5.5v. reference frequency = 4mhz. these characteristics are guaranteed by either production test or design. they apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. characteristics pin value units conditions min typ max supply current, i cc 12 68 85 ma v cc = 5v prescaler enabled, pe = 1 58 73 ma v cc = 5v prescaler disabled, pe = 0 rf input voltage 13, 14 40 300 mv rms 300mhz to 2.7ghz prescaled enabled, pe = 1, see fig. 7b. 13, 14100 300 mv rms 80mhz prescaler enabled, pe=1, see fig. 7b. 13,14 50 300 mv rms 80mhz to 2.0ghz prescaler disabled, pe = 0, see fig. 7a. rf input impedance 13, 14 50 ? refer to fig. 13 rf input capacitance 13, 14 2 pf refer to fig. 13 sda, scl 5, 6 input high voltage 3 5.5 v input low voltage 0 1.5 v input high current 10 a input voltage = v cc input low current 10 a input voltage = v ee leakagecurrent 10 av cc = v ee input hysteresis 0.8 v sda output voltage 5 0.4 v i sink = 3ma charge pump output 1 see fig. 6, v pin = 2v current charge pump output 1 3 10 na v pin1 = 2v leakage charge pump drive output current 16 1 mav pin16 = 0.7v drive output saturation voltage when disabled 16 350 mv external reference input frequency 2 2 20 mhzac coupled sinewave external reference input ampltude 2 200 500 mv p pac coupled sinewave crystal frequency 2 4 16 mhz crystal oscillator drive 2 35 mv p p level recommended crystal series resistance 10 200 ? applies to 4mhz crystal only. parallel resonant crystal. figure quoted is under all conditions including start up. crystal oscillator negative resistance 2 400 ? includes temperature and process tolerances. ref/comp output 3 voltage 350 mv p p ac coupled output. output enabled,re=1. see note 1.
4 SP5669 preliminary information electrical chacteristics (cont.) t amb = 20 c to 80 c, v cc = + 4.5v to + 5.5v. reference frequency = 4mhz. these characteristics are guaranteed by either production test or design. they apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. characteristics pin value units conditions min typ max comparison frequency 2 mhz equivalent phase noise at phase detector 148 dbc/hz 6khz loop bw, phase comparator freq 250khz. figure measured @ 1khz offset, ssb (within loop band width). rf division ratio 240 131071 prescaler disabled, pe = 0 480 262142 prescaler enabled, pe = 1 reference division ratio see fig. 3 output ports p0, p1, p2, p3 7,8,9, 10 sink current 10 ma v port = 0.7v leakage current 10 a v port = 13.2v adc input voltage 11 see table 4, fig 4 adc input current 11 10 av cc v input v ee address input current high 4 1 ma input voltage =v cc address input current low 4 0.5 ma input voltage =v ee note 1: if the ref/comp output is not used, the output should be left open circuit or connected to v cc , and disabled by setting re=0. absolute maximum ratings all voltages are referred to v ee at 0v. characteristics pin value units conditions min max supply voltage, v cc 12 0.3 7 v rf input voltage 13,14 2.5 v p p ac coupled as per application rf input dc offset 13,14 0.3 v cc +0.3 v port voltage 7 10 0.3 14 v port in off state 7 10 0.3 6 v port in on state total port current 7 10 50 ma adc input dc offset 11 0.3 v cc +0.3 v ref/comp output dc offset 3 0.3 v cc +0.3 v charge pump dc offset 1 0.3 v cc +0.3 v drive dc offset 16 0.3 v cc +0.3 v crystal oscillator dc offset 2 0.3 v cc +0.3 v address dc offset 4 0.3 v cc +0.3 v sda and scl dc offset 5, 6 0.3 6v v storage temperature 55 +150 c junction temperature +150 c mp16 thermal resistance chip to ambient 111 c/w chip to case 41 c/w power consumption at v cc =5.5v 468 mw all ports off, prescaler enabled esd protection all 4 kv mil std 883 tm 3015
5 SP5669 preliminary information functional description the SP5669 contains all the elements necessary, with the exception of a frequency reference, loop filter and external high voltage transistor, to control a varicap tuned local oscillator, so forming a complete pll frequency synthesised source. the device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. the block diagram is shown in fig. 2. the rf input signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. the output of the preamplifier interfaces with the 17 bit fully programmable divider via a divide by two prescaler. for applications up to 2ghz rf input, the prescaler may be disabled so eliminating the degradation in phase noise due to prescaler action. the divider is of mn+a architecture, where the dual modulus prescaler is 16/17, the a counter is 4 bits, and the m counter is 13 bits. the output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. this frequency is derived either from the on board crystal controlled oscillator or from an external reference source. in both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into 1 of 15 ratios as detailed in fig. 3. the output of the phase detector feeds a charge pump and loop amplifier section, which when used with an external voltage transistor and loop filter, integrates the current pulses into the varactor line voltage. by invoking the device test modes as described in fig. 5, the varactor drive output can be disabled so switching the external transistor off and allowing an external voltage to be written to the varactor line for tuner alignment purposes. similarly, the charge pump may be also disabled to a high impedance state. the programmable divider output fpd/2 can be switched to port p0 by programming the device into test mode. the test modes are described in fig. 5 high programming the SP5669 is controlled by an i 2 c data bus. data and clock are fed in on the sda and scl lines respectively as defined by i 2 c bus format. the synthesiser can either accept data (write mode) or send data (read mode). the lsb of the address byte (r/w) sets the device into write mode if it is low, and read mode if it is high. tables 1 and 2 in fig. 4 illustrate the format of the data. the device can be programmed to respond to several addresses, which enables the use of more than one synthesiser in an i 2 c bus system. table 3 in fig.4 shows how the address is selected by applying a voltage to the address input. when the device receives a valid address byte, it pulls the sda line low during the acknowledge period, and during following acknowledge periods after further data bytes are received. when the device is programmed into read mode, the controller accepting the data must pull the sda line low during all status byte acknowledge periods to read another status byte. if the controller fails to pull the sda line low during this period, the device generates an internal stop condition, which inhibits further reading. write mode with reference to table 1, bytes 2 and 3 contain frequency information bits 2 14 2 0 inclusive. auxillary frequency bits 2 16 2 15 are in byte 4. for most frequencies only bytes 2 and 3 will be required. the remainder of byte 4 and byte 5 control the prescaler enable, reference divider ratio (see fig. 3), charge pump, ref/comp output (see fig. 5), output ports and test modes (see fig. 5). after reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines whether the byte is interpreted as a byte 2 or 4, a logic 0 indicating byte 2 and a logic 1 indicating byte 4. having interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively. having received two complete data bytes, additional data bytes can be entered, where byte interpretation follows the same procedure, without readdressing the device. this procedure continues until a stop condition is received. the stop condition can be generated after any data byte, if however it occurs during a byte transmission, the previous data is retained.
6 SP5669 preliminary information to facilitate smooth fine tuning, the frequency data bytes are only accepted by the device after all 17 bits of frequency data have been received, or after the generation of a stop condition. repeatedly sending bytes 2 and 3 only will not change the frequency. a frequency change occurs when one of the following data sequences is sent to an addressed device; bytes 2, 3, 4, 5 bytes 4, 5, 2, 3 or when a stop condition follows valid data bytes as follows; bytes 2, 3, 4, stop bytes 4, 5, 2 stop bytes 2, 3, stop bytes 2, stop bytes 4, stop it should be noted that the device must be initially addressed with both frequency and control byte data, since the control byte contains reference divider information which must be provided before a chosen frequency can be synthesised. this implies that after initial turn on, bytes 2, 3, 4 must be sent followed by a stop condition as a minimum requirement. alternatively bytes 2, 3, 4, 5 must be sent if port information is also required. read mode when the device is in read mode, the status byte read fromthe device takes the form shown in table 2, fig. 4. bit 1 (por) is the power on reset indicator, and this is set to a logic 1 if the v cc supply to the device has dropped below 3v (at 25 c), e.g. when the device is initially turned on. the por is reset to 0 when the read sequence is terminated by a stop command. when por is set high (at low v cc ), the programmed information is lost and the output ports are all set to high impedance. bit 2 (fl) indicates whether the device is phase locked, a logic 1 is present if the device is locked, and a logic 0 if the device is unlocked. bits 6,7 and 8 (a2, a1, a0) combine to give the output of the adc. the adc can be used to feed afc information to the microprocessor via the i 2 c bus. additional programmable features prescaler enable the divide by two prescaler is enabled by setting bit pe within byte 4 to a logic 1 . a logic 0 disables the prescaler, directly passing the rf input frequency to the 17 bit programmable counter. bit pe is a static select only. charge pump current the charge pump current can be programmed by bits c1 and c0 within data byte 5, as defined in fig. 6. test mode the test modes are invoked by setting bits re=0 and rts=1 within the programming data, and are selected by bits ts2, ts1 and ts0 as shown in fig. 5. when ts2, ts1 and ts0 are received, the device retains previously received p2, p1 and p0 data. reference/comparison frequency output the reference frequency f ref can be switched to the ref/comp output, pin 3, by setting bit re=1 and rts=0 within byte 5. the comparison frequency f comp can be switched to the ref/comp output, pin 3, by setting bit re=1 and rts=1 within byte 5. for re set to logic 0 , the output is disabled and set to a high state. re and rts default to logic 1 during device power up, thus enabling the comparison frequency f comp at the ref/comp output . comparison frequency with a r3 r2 r1 r0 ratio 4mhz external reference 0 0 0 0 2 2mhz 0001 4 1mhz 0 0 1 0 8 500khz 0011 16 250khz 0100 32 125khz 0101 64 62.5khz 0100 128 31.25khz 0111 256 15.625khz 1 0 0 0 not - allowed 1001 6 666.67khz 1010 12 333.33khz 1011 24 166.67khz 1100 48 83.33khz 1101 96 41.67khz 1110 192 20.83khz 1111 384 10.42khz figure 3 - reference division ratios
7 SP5669 preliminary information a : acknowledge bit ma1, ma0 : variable address bits (see table 3) 2 16 2 0 : programmable division ratio control bits pe : prescaler enable r3,r2,r1,r0 : reference division ratio select (see fig. 3) c1, c0 : charge pump current select (see fig.6) re : reference oscillator output enable rts : ref/comp output select when re=1 (see fig.5) rts : test mode enable when re=0 (see fig.5) ts2, ts1, ts0 : test mode control bits (valid when re=0, rts=1, see fig. 5) p0 : p0 port output state (always valid except when re=0, rts=1) p3, p2, p1 : p3, p2 and p1 port output states por : power on reset indicator fl : phase lock flag a2, a1, a0 : adc data (see table 4) x : don t care a2 a1 a0 voltage on adc input 1 0 0 0.6v cc tov cc 0 1 1 0.45v cc to 0.6v cc 0 1 0 0.3v cc to 0.45v cc 0 0 1 0.15v cc to 0.3v cc 0 0 0 0 to 0.15v cc table 4 - adc levels figure 4 - data formats msb lsb address 1 1 0 0 0 ma1 ma0 0 a byte 1 programmable divider 0 2 14 2 13 2 12 2 11 2 10 2 9 2 8 a byte 2 programmable divider 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 a byte 3 control data 1 2 16 2 15 pe r3 r2 r1 r0 a byte 4 control data c1 c0 re rts p3 p2/ts2 p1/ts1 p0/ts0 a byte 5 table 1 - write data format (msb is transmitted first) msb lsb address 1 1 0 0 0 ma1 ma0 1 a byte 1 status byte por fl x x x a2 a1 a0 a byte 2 table 2 - read data format (msb is transmitted first) ma1 ma0 address input voltage level 00 0 0.1v cc 0 1 open circuit 1 0 0.4v cc 0.6v cc # 1 1 0.9v cc v cc # programmed by connecting a 15k ? resistor between pin 4 and v cc table 3 - address selection
8 SP5669 preliminary information re rts ts2 ts1 ts0 ref/comp output test mode description mode 0 0 x x x disabled to high state normal operation 0 1 x 0 0 disabled to high state charge pump sink. status byte fl = logic 1 0 1 x 0 1 disabled to high state charge pump source. status byte fl = logic 0 0 1 x 1 0 disabled to high state charge pump disabled. status byte fl=logic 0 0 1 x 1 1 disabled to high state port p0 = f pd /2 0 1 1 x x disabled to high state varactor drive output disabled 1 0xxx f ref switched normal operation 1 1xxx f comp switched normal operation x=don t care figure 5 - ref/comp output mode and test modes c1 c0 current in a byte 5, bit 1 byte 5, bit 2 min typ max 0 0 90 120 150 01 195 260 325 1 0 416 555 694 11 900 1200 1500 figure 6 - charge pump current 300 100 50 10 1000 2000 3000 frequency (mhz) 3500 operating window 1000 2000 2700 3000 frequency (mhz) 3500 300 operating window 300 100 50 10 vin (mv rms int o 50 ) vin (mv rms int o 50 ) 100 80 80 figure 7a - typical input sensitivity (prescaler disabled, pe=0) figure 7b - typical input sensitivity (prescaler enabled, pe=1)
9 SP5669 preliminary information double conversion tuner systems the high 2.7ghz maximum operating frequency and excellent noise characteristics of the SP5669 enables the construction of double conversion high if tuners. a typical system shown in fig.8 will use the SP5669 as the first lo control for full band upconversion to an if of greater than 1ghz. the wide range of reference division ratios allows the SP5669 to be used both for the up converter lo with a high phase comparator frequency (hence low phase noise) and the down converter which utilises the device in a lower comparison frequency mode (which offers a fine step size). 50?00mhz 1.6ghz 38.9mhz 1650?700mhz sp5659 sp5659 first lo second lo reference clock figure 8 - example of double conversion from vhf/uhf frequencies to tv if control micro 15nf 68pf +30v +5v 22k 16k 47k +12v 2n2 bcw31 1n 1n 10n p3 tuner oscillator output sp5659 13k3 p0 scl sda address ref 10n 18pf 4mhz optional application utilising on board crystal controlled oscillator 2 3 4 5 6 7 13 12 11 10 89 116 116 14 15 p2 p1 adc figure 9 - typical appliction application notes a generic set of application notes an168 for designing with synthesisers such as the sp5659 has been written. this covers aspects such as loop filter design and decoupling. this application note is also featured in the media data book, or refer to the zarlink semicondor internet site http://www.zarlink.com. a generic test/demo board has been produced which can be used for the SP5669. a circuit diagram and list of components for the board is shown in figs. 10 and 11. the board can be used for the following purposes: (a) measuring rf sensitivity performance. (b) indicating port function. (c) synthesising a voltage controlled oscillator. (d) testing of external reference SP5669 SP5669 SP5669
10 SP5669 preliminary information figure 10 - test board . external reference skt2 10nf* *(not fitted) c6 c2 15nf r6 13k3 c3 68pf +5v p2 +12v c8 c9 c7/c8/c9 = 100nf r7 22k c7 r8 16k r9 47k c12 2n2f var gnd t1 2n3904 13 12 11 10 9 8 2 3 4 5 6 7 c5 1nf c4 1nf skt1 rf input c10 1nf r5 4k7 d5 d4 d3 d2 d1 r4 4k7 r3 4k7 r2 4k7 r1 4k7 c11 1nf c1 18pf x1 4mhz p1 c13 100pf c14 100pf disable / ref enable data / sda clock / scl +30v lock 1 1 14 15 16 note : the circuit diagram shown is designed for use with a number of synthesisers. the led connected to pin 1 1 is redundant when a sp5659 is used in this board. SP5669 figure 11 - test board (layout)
11 SP5669 preliminary information there are two ways of achieving a higher phase compa- rator sampling frequency: a) reduce the division ratio between the reference source and the phase comparator b) use a higher reference source frequency. approach b) may be preferred for best performance since it is possible that the noise floor of the reference oscillator may degrade the phase comparator perform- ance if the reference division ratio is very small. driving two devicesfrom a common reference as mentioned earlier in the datasheet, the SP5669 has a ref/comp output which allows two synthesisers to be driven from a common reference. to do this, the master should be programmed by setting re = 1 and rts = 0. the driven device should be programmed for normal operation i.e. re = 0, and rts = 0. the two devices should be connected as shown below. ( ) loop bandwidth the majority of applications for which the SP5669 is intended require a loop filter bandwidth of between 2khz and10khz. typically the vco phase noise will be specified at both 1khz and10khz offset. it is common practice to arrange the loop filter bandwidth such that the 1khz figure lies within the loop bandwidth. thus the phase noise de- pends on the synthesiser comparator noise floor, rather than the vco. the 10khz offset figure should depend on the vco providing the loop is designed correctly, and is not underdamped. reference source the SP5669 offers optimal lo phase noise perform- ance when operated with a large step size. this is due to the fact that the lo phase noise within the loop bandwidth is: phase comparator lo frequency noise floor + 20 log 10 phase comparator frequency assuming the phase comparator noise floor is flat irrespective of sampling frequency, this means that the best performance will be achieved when the overall lo to phase comparator division ratio is a minimum.
12 SP5669 preliminary information SP5669 SP5669 4mhz 18pf 1nf sp5659 2 3 4 5 6 7 13 12 11 10 89 14 15 116 116 sp5659 2 3 4 5 6 7 13 12 11 10 89 14 15 116 116 figure 12 - driving two devices from a common reference 0.5 0.2 1 0 +j0.2 +j0.5 +j1 +j2 +j5 2 5 j5 j2 j1 j0.5 j0.2 frequency markers a t 100mhz, s 11 :z 0 = 50 x x x x normalised t o 50 500mhz, 1ghz and 2.7ghz figure 13 - typical rf input impedance
13 SP5669 preliminary information v ref 500 500 rf inputs v cc charge pump drive output port crystal rf inputs loop amplifier sda and scl and adc reference oscillator output ports 100 os (output disable) v cc 200 v cc 3k scl/sda/adc ack sda onl y v cc 30k 3k 10k address address input ref/comp output v cc ref/comp enable/ disable figure 14 - input/output interface circuits

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